Synthesis refers to the process of converting, or translating, an abstract, programmatic description of a circuit into a low-level design implementation. The abstract, programmatic description of the circuit describes behavior of the circuit and is also referred to as a “behavioral description” or a “register transfer level (RTL) description” of the circuit. The behavioral description is often specified using a hardware description language (HDL). The low-level design implementation generated through synthesis typically is specified as inter-connected logic gates.
High-level synthesis or “HLS” is an automated design process in which a description of desired behavior of a system is converted into a circuit design and/or digital circuitry. The description of the desired behavior is typically written as an application in a high level programming language such as C, C++, OpenCL™, and so forth. The application may be translated into a circuit design that may be specified as an RTL description. The RTL description describes a synchronous digital circuit in terms of the flow of digital signals between hardware registers and the operations performed on those signals. The RTL description may be further translated into a low-level design implementation.
A synthesized circuit design may be further processed through one or more additional phases of a design flow. Further, the processed circuit design may be implemented within an integrated circuit (IC). In a synthesized circuit design, many design tools utilize fixed delays to characterize the timing of nets of the circuit design since so little information about the ultimate physical implementation and/or architecture of the circuit design is known. In many cases, these delay estimates are overly optimistic. In consequence, the design tools often fail to place and route the circuit design meaning that the placed and/or routed circuit fails to meet established timing requirements for the circuit design and for the resulting physical circuit implementation within the target IC.